There are a variety of analog-to-digital ("A/D") converters. For example, there are parallel encoder (or flash) A/D converters, multistage A/D converters, successive approximation A/D converters, voltage-to-frequency A/D converters, dual-ramp A/D converters, and staircase A/D converters. There is such a variety because the need for converters has heightened with the advent of single-chip large scale integration ("LSI") microprocessors. In fact, in some cases, it is desirable to include such converters on the same chip with the microprocessor.
In many cases, there is the desire to have very fast conversion to maintain the speed of the overall system. The types of A/D converters typically used in these situations have been flash and multistage A/D converters. As larger and larger flash A/D converters were being constructed, the resulting large dies had a great deal of parasitics that had to be driven. This forced the technology in the opposite direction, which was to make the A/D converters smaller and smaller. This brought about the advent of the consideration of replacing flash and multistage flash A/D converters with serial-type A/D converters because in many ways they were easier to construct on a chip than multistage flash A/D converters and, in some cases, achieve the speed off flash A/D converters at considerably less power.
Serial-type A/D converters typically convert analog signals first into Gray scale code and then into binary code. They are configured to have a series of cascaded analog cells to which the Gray scale code-to-binary processing system connects. Each cell of the series of cascaded analog cells has a folding cell that will process the differential input signals, V.sub.INN and V.sub.IN, according to FIG. 1A.
The signals input to the differential input of the folding cell are shown in FIG. 1A. As V.sub.IN increases and V.sub.INN decreases, there is a single crossing at 100. This is the input level where the comparator of the folding cell is tripped and the V.sub.IN and V.sub.INN signals are folded to form the intermediate signals V.sub.MAG and V.sub.MAGN that are shown in FIG. 1B. A Gray scale digital word is derived from the outputs of the comparator. These intermediate signals are output from the current switching portion of the folding cell. When V.sub.MAG and V.sub.MAGN are folded as shown in FIG. 1B, the folded signals converge but do not cross, as shown at 102.
In order to obtain the desired V.sub.O and V.sub.ON outputs for input to the next stage, it is necessary to further process the V.sub.MAG and V.sub.MAGN signals. The V.sub.MAG signal must be positive offset one-quarter of full scale and the V.sub.MAGN signal must be negative offset one quarter of full scale to align the signals. Once the offset has been applied, the alignment shown in FIG. 1C results. This alignment has crossing points at 104 and 106. Thereafter, the V.sub.O and V.sub.ON signals are input to the next stage of the serial-type A/D converter.
Since the analog folding is done independently from the digital Gray scale outputs all digital latching can be done in parallel.
The folding cells of serial-type A/D converters have taken many configurations, one of which is a magnitude amplifier ("magamp") with offset circuitry that either is incorporated directly as part of the magamp or is separate circuitry that connects to the magamp. In order to maximize the speed of the conversion, it is necessary to design the magamps to operate as fast as possible.
The speed of the magamp rests in many cases on the operation of the folding cell. This speed also is affected by the ability of the input transistors to process the input signals. Therefore, an improvement of the configuration of the input transistors can increase the speed of the magamp.
The present invention provides a faster magamp, as will be described in detail in the remainder of the specification, referring to the drawings.